NEGF simulations of the effect of strain on scaled double gate nanoMOSFETs

The effect of biaxial strain on double gate (DG) nanoscaled Si MOSFET with channel lengths in the nanometre range is investigated using Non-Equilibrium Green’s Functions (NEGF) simulations. We have employed fully 2D NEGF simulations in order to answer the question at which body thickness the effects of strain is masked by the confinement impact. Following ITRS, we start with a 14 nm gate length DG MOSFET having a body thickness of 9 nm scaling the transistors to gate lengths of 10, 6 and 4 nm and body thicknesses of 6.1, 2.6 and 1.3 nm. The simulated I _D–V _G characteristics show a 6% improvement in the on-current for the 14 nm gate length transistor mainly due to the energy separation of the Δ valleys. The strain effect separates the 2 fold from the 4 fold valleys thus keeping mostly operational transverse electron effective mass in the transport direction. However, in the device with an extreme body thickness of 1.3 nm, the strain effect has no more impact on the DG performance because the strong confinement itself produces a large energy separation of valleys.     

Effect of doping concentration on the grain boundary trap density and threshold voltage of polycrystalline SOI MOSFETs

PolySOI MOSFETs have been fabricated on undoped and doped polycrystalline silicon films and characterized to study the effect of doping on grain boundary passivation. The grain boundary trap density (N_ST) and threshold voltages have been extracted experimentally to evaluate the extent of grain boundary passivation by the dopants. Charge sheet model based on the effective doping concentration has been employed to analytically estimate the threshold voltages using the experimentally determined grain boundary trap density and grain size (L_g) as model parameters. The variation of threshold voltages with increasing doping concentration for the range of N_A ? (N_ST/L_g) has been studied both by simulation and experiments and the results are presented. Analytically estimated threshold voltages and experimental results show that the threshold voltage falls with increase in the dopant concentration and that this effect is indeed due to the reduction in N_ST as a result of the grain boundary passivation by the dopants.     

Ultra-shallow raised p+−n junctions formed by diffusion from selectively depositedIn-situ doped Si0.7Ge0.3

In this paper, a novel raised p⁺−n junction formation technique is presented. The technique makes use ofin- situ doped, selectively deposited Si_0.7Ge_0.3 as a solid diffusion source. In this study, the films were deposited in a tungsten halogen lamp heated cold-walled rapid thermal processor using SiCl₂H₂, GeH₄, and B₂H₆. The microstructure of the Si_0.7Ge_0.3 layer resembles that of a heavily defected epitaxial layer with a high density of misfit dislocations, micro-twins, and stacking faults. Conventional furnace annealing or rapid thermal annealing were used to drive the boron from thein- situ doped Si_0.7Ge_0.3 source into silicon to form ultra-shallow p⁺−n junctions. Segregation at the Si_0.7Ge_0.3/Si interface was observed resulting in an approximately 3:1 boron concentration discontinuity at the interface. Junction profiles as shallow as a few hundred angstroms were formed at a background concentration of 10¹⁷ cm⁻³.     

Synchrotron x-ray irradiation effects on the device characteristics and the resistance to hot-carrier damage of MOSFETs with 4 nm thick gate oxides

The effects of synchrotron x-ray irradiation on the device characteristics and hot-carrier resistance of n- and p-channel metal oxide semiconductor field effect transistors (MOSFETs) with 4 nm thick gate oxides are investigated. In p-channel MOSFETs, device characteristics were significantly affected by the x-ray irradiation but completely recovered after annealing, while the device characteristics in n-channel MOSFETs were not noticeably affected by the irradiation. This difference appears to be due to a difference in interface-state generation. In p-channel MOSFETs, defects caused by boron-ion penetration through the gate oxides may be sensitive to x-ray irradiation, causing the generation of many interface states. These interface states are completely eliminated after annealing in hydrogen gas. The effects of irradiation on the resistance to hot-carrier degradation in annealed 4 nm thick gate-oxide MOSFETs were negligible even at an x-ray dose of 6000 mJ/cm².     

A comprehensive geometrical and biasing analysis for latchup in 0.18-μm CoSi2 STI CMOS structure

This paper evaluates the effects of dimension variations on the latchup immunity of 0.18-μm CoSi₂ shallow trench isolation (STI) CMOS structures. A comprehensive study on the test devices, by variations of geometrical dimensions as well as the spacings, has been established. Focus has also been given to the dimensions of the STI structure, mainly on the width and depth, as the rest of the parameters are varied. The influence of biasing condition on latchup has also been investigated. The results obtained and the as-developed characterization techniques shall bestow a CMOS device that promises optimized layout dimension.     

Effect of elastic processes and ballistic recovery in silicon nanowire transistors

Scaling of silicon devices is fast approaching the limit where a single gate may fail to retain effective control over the channel region. Of the alternative device structures under focus, silicon nanowire transistors (SNWT) show great promise in terms of scalability, performance, and ease of fabrication. Here we present the results of self-consistent, fully 3D quantum mechanical simulations of SNWTs to show the role of surface roughness (SR) and ionized dopant scattering on the transport of carriers. We find that the addition of SR, in conjunction with impurity scattering, causes additional quantum interference which increases the variation of the operational parameters of the SNWT. However, we also find that quantum interference and elastic processes can be overcome to obtain nearly ballistic behavior in devices with preferential dopant configurations.     

一种性能优良稳定的微功耗CMOS电压积分器

本文提出了一种电源波动影响弱、低温飘、微功耗（〈1μw）的CMOS电压型积分器电路。它利用自偏置的恒流源电路结构以及MOSFETs的亚阈值特性产生一个nA级的恒流源，通过控制电路实现对电容充放电来获得积分电压。并且对电路结构、器件类型和器件尺寸进行了优化。仿真结果表明，得到了独立于电源电压、低温度系数、微功耗的积分电压。     

Subthreshold surface potential and drain current models for short-channel pocket-implanted MOSFETs

An analytical subthreshold surface potential model for short-channel pocket-implanted (double-halo) MOSFET is presented. The effect of the depletion layers around the source and drain junctions on channel depletion layer depth, which is very important for short-channel devices, is included. Using this surface potential, a drift-diffusion based analytical subthreshold drain current model for short-channel pocket-implanted MOSFETs is also proposed. A physically-based empirical modification of the channel conduction layer thickness that was originally proposed for relatively long-channel conventional device is made for such short-channel double-halo devices. Very good agreement for both the surface potential and drain current is observed between the model calculation and the prediction made by the 2-D numerical device simulation using Dessis.